Renesas M16C/29 Series Hardware Manual page 50

M16C/29 Group
V
CC
ROC
td(P-R)
RESET
CPU clock
Address
Figure 5.1.1.2. Reset Sequence
Table 5.1.1.1. Pin Status When RESET Pin Level is "L"
Pin name
P0 to P3,
P6 to P10
b15
IPL
Figure 5.1.1.3. CPU Register Status After Reset
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
More than
td(ROC)
CPU clock
____________
Status
Input port (high impedance)
b15
0000
0000
0000
0000
0000
0000
0000
b19
00000
16
Content of addresses FFFFE
b15
0000
0000
0000
b15
0000
b8 b7
U I
page 30 of 402
28cycles
FFFFC Content of reset vector
16
FFFFE
16
b0
16 Data register(R0)
16 Data register(R1)
Data register(R2)
16
16 Data register(R3)
16
Address register(A0)
16
Address register(A1)
16
Frame base register(FB)
b0
Interrupt table register(INTB)
to FFFFC
16 16
Program counter(PC)
b0
User stack pointer(USP)
16
16
Interrupt stack pointer(ISP)
16
Static base register(SB)
b0
16
b0
O B S Z D C
Flag register(FLG)
5. Reset