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M16C/29 Group
2
16.6 I
C0 control register 1 (S3D0 register)
2
I
C0 control register 1 (address 02E6
16.6.1 Bit 0 : Interrupt enable bit by STOP condition (SIM )
This bit enables the I
condition. If the bit set to "1", an interrupt request from the I
STOP condition ( There is no change for the PIN flag)
16.6.2 Bit 1: Interrupt enable bit at the completion of data receive (WIT)
When with ACK mode (ACK bit = 1) is specified, by the interrupt enable (WIT bit = 1) at the completion of
data receive, the I
nized with the falling edge of the last data bit clock. The SCL becomes "L" and the ACK clock generation
is suppressed.
Table 16.4 and Figure 16.12 show the I
method. After the communication restart, synchronized with the falling edge of ACK clock, the PIN bit
becomes "0" again and the I
Table16.4 Timing of interrupt generation in data receive
2
I
C bus interrupt generation timing
1) Synchronized with the falling edge of the
last data bit clock
2) Synchronized with the falling edge of the
ACK clock
The state of the internal WAIT flag can be read out by reading the WIT bit. The internal WAIT flag is set after
2
writing to the I
C0 data shift register, and it is reset after writing to the I
2
quently, the I
C bus interface interrupt request generated by the timing 1) or 2) can be determined. (See
Figure 16.12 The timing of the interrupt generation at the competion of data receive.) In the cases of
transmit and the address data receive immediately after the START condition, the I
request is only generated at the falling edge of the ACK clock regardless of the value of the WIT bit and the
WAIT flag remains the reset state. Write "0" to the WIT bit when in NACK is specified. (ACK bit = 0)
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
) controls I
16
2
C bus interface to request an I
2
C bus interface interrupt request is generated and the PIN bit becomes "0" synchro-
2
2
C bus interface interrupt request is generated.
page 264 of 402
2
C bus interface circuit.
2
C bus interface interrupt by detecting a STOP
2
C bus interface is generated by detecting a
C bus interrupt request timing and the communication restart
Communication restart method
The execution of writing to ACK bit of I
register. Follow this by a register write to set PIN bit = 1.
(Do not write to the I
The ACK clock operation can be incorrect.)
The execution of writing to the I
2
16. MULTI-MASTER I
C bus INTERFACE
2
C0 clock control
2
C0 data shift register.
2
C0 data shift register
2
C0 clock control register. Conse-
2
C bus interface interrupt
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