Renesas M16C/29 Series Hardware Manual page 237

16-bit single-chip microcomputer
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M16C/29 Group
A/D trigger control register (Note 1, 2)
b7
b6
b5
b4
b3
b2
Note 1: If the ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: Set "00
16
sweep mode 1.
Figure 15.3 ADTRGCON Register
Table 15.2 A/D Conversion Frequency Select
CKS2
CKS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Note: Set the Ø
AD
the CKS0 bit in the ADCON0 register, CKS1 bit in the ADCON1 register and the CKS2 bit in the ADCON2
register.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b1
b0
Symbol
ADTRGCON
Bit symbol
A/D Operation Mode
SSE
Select Bit 2
A/D Operation Mode
DTE
Select Bit 3
AN0 Trigger Select Bit
HPTRG0
AN1 Trigger Select Bit
HPTRG1
Nothing is assigned. When write, set to "0".
(b7-b4)
When read, its content is "0".
" in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat
CKS0
Ø
0
Divided-by-4 of f
AD
1
Divided-by-2 of f
AD
0
f
AD
1
0
Divided-by-12 of f
1
Divided-by-6 of f
AD
0
Divided-by-3 of f
AD
1
frequency to 10 MHz or less. The selected Ø
page 217 of 402
Address
After reset
03D2
00
16
16
Bit name
0 : Other than simultaneous sample sweep
mode or delayed trigger mode 0,1
1 : Simultaneous sample sweep mode or
delayed trigger mode 0,1
0 : Other than delayed trigger mode 0,1
1 : Delayed trigger mode 0,1
Function varies with each operation mode
Function varies with each operation mode
AD
AD
frequency is determined by a combination of
AD
15. A/D Converter
Function
RW
RW
RW
RW
RW

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