Renesas M16C/29 Series Hardware Manual page 192

M16C/29 Group
UART2 special mode register 3
b7 b6 b5 b4 b3 b2 b1 b0
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I
mode, set these bits to "000
Note 2 : The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
UART2 special mode register 4
b7 b6 b5 b4 b3 b2 b1 b0
Note: Set to "0" when each condition is generated.
Figure 14.1.9. Serial I/O-related registers (6)
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Symbol
U2SMR3
Bit
Bit name
symbol
Nothing is assigned.
(b0)
When write, set "0". When read, its content is indeterminate.
CKPH Clock phase set bit
Nothing is assigned.
(b2)
When write, set "0". When read, its content is indeterminate.
NODC Clock output select bit
Nothing is assigned.
(b4)
When write, set "0". When read, its content is indeterminate.
DL0
SDA digital delay
setup bit
(Note 1, Note 2)
DL1
DL2
" (no delay).
2
Symbol
U2SMR4
Bit
Bit name
symbol
Start condition
STAREQ
generate bit (Note)
Restart condition
RSTAREQ
generate bit (Note)
Stop condition
STPREQ
generate bit (Note)
STSPSEL
SCL,SDA output
select bit
ACKD ACK data bit
ACK data output
ACKC
enable bit
SCL output stop
SCLHI
enable bit
SCL wait bit 3
SWC9
page 172 of 402
Address After reset
0375 000X0X0X
16
Function
0 : Without clock delay
1 : With clock delay
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
b7 b6 b5
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Address After reset
0374 00
16 16
Function
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Start and stop conditions not output
1 : Start and stop conditions output
0 : ACK
1 : NACK
0 : Serial I/O data output
1 : ACK data output
0 : Disabled
1 : Enabled
0 : SCL "L" hold disabled
1 : SCL "L" hold enabled
14.1 UARTi (i=0 to 2)
2
RW
RW
RW
RW
RW
RW
2 2
C mode. In other than I C
RW
RW
RW
RW
RW
RW
RW
RW
RW