Renesas M16C/29 Series Hardware Manual page 278

16-bit single-chip microcomputer
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M16C/29 Group
Table 16.3 Set values of I
Setting value of CCR4 to CCR0
CCR4 CCR3 CCR2 CCR1 CCR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
Note 1: The duty of the S
clock mode is selected and the CCR value = 5 (400 kHz, at VIIC = 4 MHz). "H" duration of
the clock fluctuates from –4 to +2 I
ates from –2 to +2 I
fluctuation, the frequency does not increase because the "L" is extended instead of "H" reduc
tion. These are the values when the S
not performed. The CCR value is the decimal notation value of the S
CCR4 to CCR0.
Note 2: Each value of the S
these setting values, use V
select bits (bit 6 and 7 of I
Note 3: The data formula of S
/(8 × CCR value) Standard clock mode
V
IIC
/(4 × CCR value) High-speed clock mode (CCR value ≠ 5)
V
IIC
/(2 × CCR value) High-speed clock mode (CCR value = 5)
V
IIC
Do not set 0 to 2 as the CCR value regardless of the VIIC frequency.
Set 100 kHz (max.) in standard clock mode and 400 kHz (max.) in high-speed clock
mode to the S
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
2
C0 clock control register and S
S
CL
Standard clock mode
0
0
Setting disabled
0
1
Setting disabled
1
0
Setting disabled
1
1
0
0
0
1
1
0
500 / CCR value
0
1
1
0
1
1
clock output is 50 %. The duty becomes 35 to 45 % only when high-speed
CL
2
C system clock cycles in high-speed clock mode. In the case of negative
frequency exceeds the limit at V
CL
= 4 MHz or less. Refer to Figure 16.6 I
IIC
2
C control register 1) on V
frequency is described below:
CL
frequency by setting the S
CL
page 258 of 402
16. MULTI-MASTER I
frequency
CL
frequency (at V
=4MHz, unit : kHz)
IIC
-
(Note 2)
-
(Note 2)
100
83.3
(Note 3)
17.2
16.6
16.1
2
C system clock cycles in standard clock mode, and fluctu-
clock synchronization by the synchronous function is
CL
IIC
IIC
frequency control bits CCR4 to CCR0.
CL
2
C bus INTERFACE
(Note 1)
High-speed clock mode
Setting disabled
Setting disabled
Setting disabled
333
250
400
(Note 3)
166
1000 / CCR value
(Note 3)
34.5
33.3
32.3
frequency control bits
CL
= 4 MHz or more. When using
2
C system clock
.

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