Renesas M16C/29 Series Hardware Manual page 203

M16C/29 Group
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Transfer clock
UiC1 register
"1"
TE bit
"0"
UiC1 register
TI bit "1"
"0"
"H"
CTSi
"L"
TxDi
UiC0 register
"1"
TXEPT bit
"0"
"1"
SiTIC register
IR bit
"0"
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 1 (parity enabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiIRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Transfer clock
"1"
UiC1 register
TE bit
"0"
"1"
UiC1 register
TI bit
"0"
TxDi
"1"
UiC0 register
TXEPT bit
"0"
"1"
SiTIC register
IR bit
"0"
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 1 (2 stop bits)
• UiC0 register CRD bit = 1 (CTS/RTS disabled)
• UiIRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 14.1.2.1. Typical transmit timing in UART mode (UART0, UART1)
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
The transfer clock stops momentarily as CTSi is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to "L".
Tc
Write data to the UiTB register
Start
bit
ST D D
D D D D
0 1 2 3 4 5
Tc
Write data to the UiTB register
Start
bit
ST D D D D D D
0 1 2 3 4 5
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program
page 183 of 402
Transferred from UiTB register to UARTi transmit register
Parity Stop
bit bit
D P SP ST D D
D D D
7
6 0 1 2 3
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
fj : frequency of UiBRG count source (f
f : frequency of UiBRG count source (external clock)
EXT
n : value set to UiBRG
i: 0 to 2
Transferred from UiTB register to UARTi
transmit register
Stop Stop
bit bit
D D D SP SP ST D D D D
7 8 0 1 2
6
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
fj : frequency of UiBRG count source (f
f : frequency of UiBRG count source (external clock)
EXT
n : value set to UiBRG
i: 0 to 2
14.1 UARTi (i=0 to 2)
Stopped pulsing
because the TE bit
= "0"
ST
D
D D D P SP
7
4 5 6
EXT
, f , f
1SIO 2SIO
D D D D D SPSP ST D
3 4 5 7 8 0
6
EXT
, f , f
1SIO 2SIO
D
D
0 1
, f )
8SIO 32SIO
D
1
, f )
8SIO 32SIO