Renesas M16C/29 Series Hardware Manual page 180

M16C/29 Group
(1) Free-running operation
(The RST1 bit is set to "1", and both RST4 and RST2 bits are set to "0")
Base timer
OUTC1j pin
G1IRj bit
G1IRk bit
The above applies to the following conditions.
The IVL bit in the G1POCRj register is set to "0" (output "L" as an initial value). The INV bit is set to "0" (no output
inverted).
Bits RST4, RST2, and RST1 of the G1BCR0 and G1BCR1 registers are set to "0" (no base timer reset). The UD1 to
UD0 bits are set to "00
(2) Base timer is reset when its value matches that of either register (a) G1PO0
(enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or (b) G1BTRR
(enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
Base timer
OUTC1j pin
G1IRj bit
G1IRk bit
The above applies to the following conditions.
The IVL bit in the G1POCRj register is set to "0" (output "L" as an initial value). The INV bit is set to "0" (no output
inverted).
The UD1 to UD0 bits are set to "00
Figure 13.5.3.1. Set/Reset Waveform Output Mode
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
FFFF
16
n
m
0000
16
n-m
f
BT1
Inverse
j=0, 2, 4, 6 k=j+1
m : Setting value of the G1POk register
G1IRj, G1IRk bits: Bits in the G1IR register
" (counter increment mode).
2
FFFF
16
p+2
n
m
0000
16
n-m
f
BT1
When setting to "0",
write "0" by program
j=2, 4, 6 k=j+1
m : Setting value of the G1POk register
p: Setting value of either register G1PO0 or G1BTRR
G1IRj, G1IRk bits: Bits in the G1IR register
" (counter increment mode).
2
page 160 of 402
13. Timer S (Input Capture / Output Compare)
65536-n+m
f
BT1
Inverse
65536
f
BT1
When setting to "0",
write "0" by program
inverse
n: Setting value of the G1POj register
p+2-n+m
f
BT1
When setting to "0",
write "0" by program
n: Setting value of the G1POj register
Return to initial
output level
Return to initial output level