Renesas M16C/29 Series Hardware Manual page 211

M16C/29 Group
2
Table 14.1.3.4. I C bus Mode Functions
Function
Factor of interrupt number
10 (Note 1) (Refer to Fig.
14.1.3.2.)
Factor of interrupt number
15 (Note 1) (Refer to Fig.
14.1.3.2.)
Factor of interrupt number
16 (Note 1) (Refer to Fig.
14.1.3.2.)
Timing for transferring data
from the UART reception
shift register to the U2RB
register
UART2 transmission
output delay
Functions of P7 pin
0
Functions of P7 pin
1
Functions of P7 pin
2
Noise filter width
Read RxD2 and SCL pin
2
levels
Initial value of TxD2 and
SDA outputs
2
Initial and end values of
SCL
2
DMA1 factor (Refer to Fig.
14.1.3.2.)
Store received data
Read received data
Note 1: If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to 1 (interrupt requested). (Refer to Notes on interrupts in Precautions.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore,
always be sure to clear the IR bit to 0 (interrupt not requested) after changing those bits.
SMD2—SMD0 bits in the U2MR register, IICM bit in the U2SMR register,
IICM2 bit in the U2SMR2 register, CKPH bit in the U2SMR3 register
Note 2: Set the initial value of SDA
Note 3: Second data transfer to U2RB register (Rising edge of SCL
Note 4. First data transfer to U2RB register (Falling edge of SCL
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Clock synchronous serial I/O
mode (SMD2 to SMD0 = 001
IICM = 0)
UART2 transmission
Transmission started or
completed (selected by U2IRS)
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
TxD2 output
RxD2 input
CLK2 input or output selected
15ns
Possible when the
corresponding port direction bit
= 0
CKPOL = 0 (H)
CKPOL = 1 (L)
UART2 reception
1st to 8th bits are stored in
U2RB register bit 0 to bit 7
U2RB register status is read
directly as is
output while the U2MR register s SMD2 to SMD0 bits = 000
2
page 191 of 402
14.1.3 Special Mode 1 (I
2
I C mode (SMD2 to SMD0 = 010
,
2
IICM2 = 0
(NACK/ACK interrupt)
CKPH = 0 CKPH = 1
(No clock delay) (Clock delay)
Start condition detection or stop condition detection
(Refer to Fig 14.1.3.4.)
No acknowledgment
detection (NACK)
Rising edge of SCL 9th bit
2
Acknowledgment detection
(ACK)
Rising edge of SCL 9th bit
2
Rising edge of SCL 9th bit
2
Delayed
SDA input/output
2
SCL input/output
2
(Cannot be used in I
200ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I
H L
Acknowledgment detection
(ACK)
1st to 8th bits are stored in
U2RB register bit 7 to bit 0
.
9th bit)
2
9th bit)
2
2
C bus mode) (UART2)
, IICM = 1)
2
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 1
CKPH = 0
(Clock delay)
(No clock delay)
UART2 transmission UART2 transmission
Rising edge of Falling edge of SCL
SCL 9th bit next to the 9th bit
2
UART2 transmission
Falling edge of SCL 9th bit
2
Falling and rising
Falling edge of
edges of SCL
SCL 9th bit
2
bit
2
C mode)
2
C mode (Note 2)
H L
UART2 reception
Falling edge of SCL 9th bi
t
2
1st to 7th bits are stored in U2RB register
bit 6 to bit 0, with 8th bit stored in U2RB
register bit 8
1st to 8th bits are
stored in U2RB
register bit 7 to bit 0
(Note 3)
Read U2RB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 (Note 4)
.
(serial I/O disabled).
2
2
9th
2