On-Chip Oscillator Clock; Pll Clock - Renesas M16C/29 Series Hardware Manual

M16C/29 Group

7.3 On-chip Oscillator Clock

This clock is supplied by a variable on-chip oscillator. This clock is used as the clock source for the CPU
and peripheral function clocks. In addition, if the PM22 bit of PM2 register is "1" (on-chip oscillator clock for
the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to
"10. Watchdog Timer • Count source protective mode").
After reset, the on-chip oscillator clock divided by 16 is used for the CPU clock. It can also be turned on by
setting the CM21 bit of CM2 register to "1" (on-chip oscillator clock), and is used as the clock source for the
CPU and peripheral function clocks. If the main clock stops oscillating when the CM20 bit of CM2 register is
"1" (oscillation stop, re-oscillation detection function enabled) and the CM27 bit is "1" (oscillation stop, re-
oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the neces-
sary clock for the microcomputer.

7.4 PLL Clock

The PLL clock is generated from the main clock by a PLL frequency synthesizer. This clock is used as the
clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL
frequency synthesizer is activated by setting the PLC07 bit to "1" (PLL operation). When the PLL clock is
used as the clock source for the CPU clock, wait t
CM11 bit in the CM1 register to "1".
Before entering wait mode or stop mode, be sure to set the CM11 bit to "0" (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to "0"
(PLL stops). Figure 7.4.1 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency=f(X
The PLC02 to PLC00 bits can be set only once after reset. Table 7.4.1 shows the example for setting PLL
clock frequencies.
Table 7.4.1. Example for Setting PLL Clock Frequencies
X
PLC02
IN
(MHz)
10 0
5 0
Note: 10MHz ≤ PLL clock frequency ≤ 20MHz.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
) X (multiplying factor set by the PLC02 to PLC00 bits PLC0 register
IN
(However, 10 MHz ≤ PLL clock frequency ≤ 20 MHz)
PLC01 PLC00
0 1
1 0
page 47 of 402
(PLL) for the PLL clock to be stable, and then set the
su
PLL clock
Multiplying factor
(MHz)(Note)
2
4
7. Clock Generation Circuit
20