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M16C/29 Group
17.1.3.7. C0CONR Register
Figure 17.12 shows the C0CONR register.
CAN0 configuration register
b7
b6
b5
b4
b3
Note: f
serves for the CAN clock. The period is decided by configuration of the CCLKi bits (i = 0 to 2) of the CCLKR register.
CAN
(b15)
b7
b6
b5
b4
b3
Figure 17.12 C0CONR Register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b2
b1
b0
Symbol
C0CONR
Bit symbol
BRP
SAM
PTS
(b8)
b2
b1
b0
Symbol
C0CONR
Bit symbol
PBS1
PBS2
SJW
page 290 of 402
Address
After reset
Indeterminate
021A
16
Bit name
Prescaler division
b3 b2 b1 b0
0 0 0 0 : Divide-by-1 of f
ratio select bits
0 0 0 1 : Divide-by-2 of f
0 0 1 0 : Divide-by-3 of f
1 1 1 0 : Divide-by-15 of f
1 1 1 1 : Divide-by-16 of f
Sampling control
0 : One time sampling
bit
1 : Three times sampling
b7 b6 b5
Propagation time
0 0 0 : 1Tq
segment control bits
0 0 1 : 2Tq
0 1 0 : 2Tq
1 1 0 : 7Tq
1 1 1 : 8Tq
Address
After reset
Indeterminate
021B
16
Bit name
Phase buffer
b2 b1b0
0 0 0 : Must not be set
segment 1
0 0 1 : 2Tq
control bits
0 1 0 : 3Tq
1 1 0 : 7Tq
1 1 1 : 8Tq
b5 b4 b3
Phase buffer
0 0 0 : Must not be set
segment 2
0 0 1 : 2Tq
control bits
0 1 0 : 3Tq
1 1 0 : 7Tq
1 1 1 : 8Tq
Resynchronization
b7 b6
0 0 : 1Tq
jump width
0 1 : 2Tq
control bits
1 0 : 3Tq
1 1 : 4Tq
17. CAN Module
Function
RW
CAN
CAN
RW
CAN
CAN
(Note)
CAN
RW
RW
Function
RW
RW
RW
RW
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