Renesas M16C/29 Series Hardware Manual page 136

M16C/29 Group
Timer Bi mode register (i= 0 to 1)
b7 b6 b5
Figure 12.2.4.1 TBiMR Register in Delayed Trigger Mode
Timer B2 special mode register
b7 b6 b5 b4
Note 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
Note 2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set
this bit to "0" (timer B2 underflow).
Note 3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5
bit to "0" (= input mode).
Note 4. Related pins are U(P8
Set the IVPCR1 bit to "0", and this forcible cutoff will be reset. If L is input to the P8
control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is "0", the target pins changes to
programmable I/O port. When the IVPCR1 bit is "1", the target pins changes to high-impedance state regardless of
which functions of those pins are used.
Note 5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode)
Note 6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the INV02
bit to "1" (three-phase motor control timer function).
Note 7. Refer to "19.6 Digital Debounce function" for the SD input
Figure 12.2.4.2 TB2SC Register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b4 b3 b2 b1 b0
Symbol
0 0 TB0MR to TB1MR
Bit symbol
TMOD0
Operation mode select bit
TMOD1
MR0
Invalid in A/D trigger mode
Either "0" or "1" is enabled
MR1
TB0MR register
MR2
Set to "0" in A/D trigger mode
TB1MR register
Nothing is assigned. When write, set to "0". When read, its
content is indeterminate
MR3
When write in A/D trigger mode, set to "0". When read in A/D
trigger mode, its content is indeterminate.
Count source select bit
TCK0
TCK1
(Note 1)
b3 b2 b1 b0
Symbol
TB2SC
Bit symbol
Timer B2 Reload Timing
PWCON
Switch Bit
Three-Phase Output Port
IVPCR1
SD Control Bit 1
Timer B0 Operation Mode
TB0EN
Select Bit
Timer B1 Operation Mode
TB1EN
Select Bit
TB2SEL Trigger Select Bit
Reserved bits
(b6-b5)
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is 0 .
), U(P8 ), V(P7
0 1
page 116 of 402
Address
039B to 039C 00XX0000
16 16
Bit name
b1 b0
0 0 : Timer mode or A/D trigger mode
b7 b6
0 0 : f or f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
Address After reset
039E X0000000
16
Bit name
0 : Timer B2 underflow
(Note 2) 1 : Timer A output at odd-numbered
0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
(Note 3, 4, 7)
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : TB2 interrupt
(Note 6)
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Must set to "0".
), V(P7 ), W(P7 ), W(P7 ). After forcible cutoff, input "H" to the P8
2 3 4 5
After reset
2
Function
2
2
Function
(Note 5)
(Note 5)
/NMI/SD pin, a three-phase motor
5
12.2 Timer B
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
/NMI/SD pin.
5