Table of Contents
Advertisement
M16C/29 Group
16.10 START condition duplicate protect function
It is necessary to verify that the bus is not in use via the BB flag before the start condition is generated.
However,when the BB flag is set to "1" because a start condition is generated by another master devices
immediately after the BB flag is verified, the start condition is suspended by the start condition duplicate
protect function. When the function starts, it works as follows:
•The start condition standby setting is disabled.
If the start condition standby has been set, release it and resets the MST and TRX bits.
2
•Writing to the I
C0 data shift register is disabled. (The start condition trigger generation is disabled)
•When the start condition generation is interrupted, sets the AL flag.
The start condition duplicate protect function is valid from the S
slave receive completion. Figure16.15 shows the duration of the start condition duplicate protect function.
S
CL
S
DA
BB flag
Figure 16.15 The duration of the start condition duplicate protect function
16.11 STOP Condition Generation Method
When the ES0 bit in the I
status register, and "0" to the BB, PIN and low-order 4 bits in the I
the standby status to generate the stop condition. The stop condition is generated after writing the dummy
2
data to the I
C0 data shift register. The stop condition generation timing is different in standard clock mode
and high-speed clock mode. Refer to Figure 16.17 STOP condition generation timing diagram, and
Table 16.8 Start/Stop generation timing table. Do not write data to the I
data shift register, before the BB flag becomes "0" after executing the instruction to generate the stop
condition. Otherwise, the stop condition waveform may not be operated normally.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
1 clock
1 bit
The duration of start condition duplicate protect
2
C0 control register is "1", writing "1" to the MST and the TRX bits in the I
page 271 of 402
DA
2 clock
3 clock
2 bit
3 bit
2
2
16. MULTI-MASTER I
falling edge of the start condition to the
8 clock
8 bit
ACK bit
C0 status register simultaneously enters
2
C0 status register and the I
C bus INTERFACE
ACK clock
2
C0
2
C0
Advertisement
Table of Contents
