Renesas M16C/29 Series Hardware Manual page 166

M16C/29 Group
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
The above applies to the following conditions.
The RST4 bit in the G1BCR0 register is set to "0" (the base timer is not reset by
matching the G1BTRR register)
The RST1 bit in the G1BCR1 register is set to "0" (the base timer is not reset by
matching the G1PO0 register)
The UD1 to UD0 bits in the G1BCR1 register are set to "00
Figure 13.1.2. Counter Increment Mode
State of a counter
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
Figure 13.1.3. Counter Increment/Decrement Mode
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
FFFF
16
C000
16
State of a counter
8000
16
4000
16
0000
16
"1"
b14 overflow signal
"0"
Base Timer interrupts
"1"
b15 overflow signal
"0"
Base Timer interrupt
FFFF
16
C000
16
8000
16
4000
16
0000
16
"1"
b14 overflow signal
"0"
Base Timer interrupts
"1"
b15 overflow signal
"0"
Base Timer interrupt
page 146 of 402
13. Timer S (Input Capture / Output Compare)
" (counter increment mode)
2