Renesas M16C/29 Series Hardware Manual page 75

M16C/29 Group
Main clock oscillation
PLL operation mode
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
CM04=1 CM04=0
PLL operation
mode
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
Sub clock oscillation
Notes:
1: Avoid making a transition when the CM20 bit is set to "1" (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting.
2: Wait for td(M-L) or the main clock oscillation stabilization time whichever is longer before switching over.
3: Switch clock after oscillation of sub-clock is sufficiently stable.
4: Change CM17 and CM16 before changing CM06.
5: Transit in accordance with arrow.
6: PLL operation mode can only be entered from high speed mode. Also, wait until the PLL clock is sufficiently stable before changing operation modes.
To select a 16 MHz or higher PLL clock, set the PM20 bit to "0" (SFR accessed with two wait states) before setting PLC07 to "1" (PLL operation).
7: PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 to "0" (PLL turned off)
before setting the PM20 bit to "1" (SFR accessed with one wait state).
8: Set the CM06 bit to "1" (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
9: When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability
High).
Figure 7.6.1.1. State Transition in Normal Mode
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Middle-speed mode
PLC07=1
High-speed mode (divide by 2)
CM11=1
(Note 6) CPU clock: f(X ) CPU clock: f(X )/2
IN IN
CM07=0 CM07=0
CM06=0 CM06=0
CM17=0 CM17=0
PLC07=0
CM11=0
CM16=0 CM16=1
(Note 7)
CM04=1
Middle-speed mode
High-speed mode
PLC07=1
(divide by 2)
CM11=1
(Note 6) CPU clock: f(X ) CPU clock: f(X )/2
IN IN
CM07=0 CM07=0
CM06=0 CM06=0
PLC07=0
CM17=0 CM17=0
CM11=0
CM16=0 CM16=1
(Note 7)
CM07=1
(Note 3)
CM05=1
(Note 1, Note 9)
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Middle-speed mode Middle-speed mode Middle-speed mode
(divide by 4) (divide by 8) (divide by 16)
CPU clock: f(X )/4
IN
CPU clock: f(X )/8 CPU clock: f(X
IN
CM07=0 CM07=0
CM07=0
CM06=0 CM06=0
CM17=1 CM17=1
CM06=1
CM16=0 CM16=1
CM04=0
Middle-speed mode Middle-speed mode Middle-speed mode
(divide by 4) (divide by 8) (divide by 16)
CPU clock: f(X )/4 CPU clock: f(X )/8 CPU clock: f(X
IN IN IN
CM07=0 CM07=0
CM07=0
CM06=0 CM06=0
CM17=1 CM17=1
CM06=1
CM16=0 CM16=1
CM07=0
(Note 2, Note 4)
Low-speed mode
CM21=0
CPU clock: f(X )
CIN
CM07=0
CM21=1
CM05=0
Low power dissipation mode
CPU clock: f(X )
CIN
CM07=0
CM06=1
CM15=1
7. Clock Generation Circuit
On-chip oscillator clock
oscillation
On-chip oscillator low power
On-chip oscillator mode
dissipation mode
CPU clock
CM21=0
CM05=0
)/16
IN (Note 8)
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
CM05=1
f(Ring)/16
CM21=1
(Note 1)
CM04=1 CM04=0
On-chip oscillator
mode
CM21=0 CPU clock
CM05=0 M0 M
)/16
(Note 8)
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM21=1
CM05=1
(Note 1)
Low-speed mode
CPU clock: f(X )
CIN
CM07=0
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM04=1 CM04=0
On-chip oscillator
low power
dissipation mode
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16