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M16C/29 Group
16.6.4 Bits 4,5 : S
These bits enableto monitor the logic value of the S
circuit. The S
bit monitors the S
DAM
The bits are read-only. When write, set to "0".
16.6.5 Bits 6,7 : I
These bits and ICK4 to ICK2 bits in the S4D0 register select the system clock (V
circuit. These bits enable to select the I
of the f
. f
can be selected from f
IIC
IIC
2
Table 16.6 I
C system clock select bits
I3CK4[S4D0]
ICK3[S4D0]
0
0
0
0
0
0
1
( Do not set the combination which is not indicated here)
16.6.6 The address receive in STOP mode/WAIT mode
2
The I
C bus interface circuit enables to receive the address data in WAIT mode when setting the CM02 bit
in the CM0 register to "0" (do not stop the peripheral function clock in wait mode) and entering WAIT mode.
2
However, the I
C bus interface circuit is not operated in STOP mode or in low power consumption mode,
2
because the I
C bus system clock V
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
/S
logic output value monitor bits S
DA
CL
output logic value. The S
DA
2
C system clock select bits ICK0, ICK1
2
C bus system clock V
or f
1
2
ICK2[S4D0]
0
0
0
0
0
0
0
1
1
0
1
1
0
0
is not supplied.
IIC
page 266 of 402
16. MULTI-MASTER I
and S
output signals from the I
DA
CL
CLM
among divisions by 2, 2.5, 3, 4, 5, 6 or 8
IIC
by setting the PCLK0 bit.
ICK1[S3D0]
ICK0[S3D0]
0
0
1
X
X
X
X
2
C bus INTERFACE
/S
DAM
CLM
2
C bus interface
bit monitors the S
output logic value.
CL
2
) of the I
IIC
2
I
C system clock
0
V
= 1/2 f
IIC
1
V
= 1/4 f
IIC
0
V
= 1/8 f
IIC
X
V
= 1/2.5 f
IIC
X
V
= 1/3 f
IIC
X
V
= 1/5 f
IIC
X
V
= 1/6 f
IIC
C bus interface
IIC
IIC
IIC
IIC
IIC
IIC
IIC
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