Renesas M16C/29 Series Hardware Manual page 64

M16C/29 Group
PLL control register 0
b7 b6 b5 b4 b3 b2
0 0 1
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: When the PM21 bit of PM2 register is "1" (clock modification disable), writing to this register has no effect.
Note 3: These three bits can only be modified when the PLC07 bit = "0" (PLL turned off). The value once written to this bit
cannot be modified.
Note 4: Before setting this bit to "1" , set the CM07 bit to "0" (main clock), set the CM17 to CM16 bits to "00
(main clock undivided mode), and set the CM06 bit to "0" (CM16 and CM17 bits enable).
CAN0 clock select register (Notes 1)
b7 b6 b5 b4 b3 b2
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: Configuration of CCLK2 to CCLK0 bits can be done only when the Reset bit of C0CTLR register = 1
(Reset/Initialization mode).
Note 3: Before setting this bit to "1"(CAN0 CPU interface in sleep), set the Sleep bit in C0CTLR register to "1"
(Sleep mode).
Figure 7.7. PLC0 Register and CCLKR register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
(Note 1, Note 2)
b1 b0 Symbol
PLC0
Bit
Bit name
symbol
PLL multiplying factor
PLC00
select bit
PLC01
PLC02
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b3)
Reserved bit
(b4)
Reserved bit
(b6-b5)
Operation enable bit
PLC07
b1 b0
Symbol
CCLKR
Bit symbol
CCLK0
CAN0 clock select bits
CCLK1
CCLK2
CAN0 CPU interface
CCLK3
sleep bit
Nothing is assigned. When write, set to "0". When read,
(b7-b4)
its content is "0".
page 44 of 402
Address After reset
001C 0001 X010
16
b2 b1b0
0 0 0: Do not set
(Note 3)
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1:
1 0 0:
1 0 1:
Do not set
1 1 0:
1 1 1:
Must set to "1"
Must set to "0"
0: PLL Off
1: PLL On
(Note 4)
Address After reset
025F 00
16 16
Bit name
b2 b1 b0
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
1 0 0: Divide-by-16
(Note 2)
1 0 1 :
1 1 0 :
1 1 1 :
0: CAN0 CPU interface operating
(Note 3) 1: CAN0 CPU interface in sleep
7. Clock Generation Circuit
2
Function
RW
RW
RW
RW
RW
RW
RW
"
2
Function
RW
RW
RW
Inhibited
RW
RW
RW