Renesas M16C/29 Series Hardware Manual page 156

M16C/29 Group
Base timer control register 1
b7 b6 b5 b4
0
Note 1: The base timer is reset after two clock cycles of f
Figure 13.8 about the G1PO0 register.) When setting the RST1 bit to "1", values of the G1POj
register (j=1 to7) to use for the waveform generation function should be set to smaller value than
values of the G1PO0 register.
Figure 13.4. G1BCR1 Register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b3 b2 b1 b0
Symbol
0 0 G1BCR1
Bit
symbol
Reserved bit
(b0)
Base timer reset
RST1
cause select bit 1
Base timer reset
RST2
cause select bit 2
Reserved bit
(b3)
Base timer
BTS
start bit
UD0
Counter increment/
decrement control bit
UD1
Reserved bit
(b7)
page 136 of 402
13. Timer S (Input Capture / Output Compare)
Address
0323
16
Bit name
Should be set to "0".
0: The base timer is not reset by
matching the G1PO0 register
1: The base timer is reset by matching
the G1PO0 register (Note 1)
0: The base timer is not reset when an
input to the INT1 pin is "L" level
1: The base timer is reset when an input
to the INT1 pin is "L" level
Should set to "0".
0: Base timer is reset
1: Base timer starts counting
b6 b5
0 0 : Counter increment mode
0 1 : Counter increment/decrement mode
1 0 : Two-phase pulse signal processing
mode
1 1 : Avoid this setting
Should set to "0".
when it matches the G1PO0 register. (See
BT1
When reset
0000 0000
2
Function RW
RW
RW
RW
RW
RW
RW
RW
RW