Clk Polarity Select Function; Lsb First/Msb First Select Function - Renesas M16C/29 Series Hardware Manual

M16C/29 Group

14.1.1.1 CLK Polarity Select Function

Use the UiC0 register (i = 0 to 2)'s CKPOL bit to select the transfer clock polarity. Figure 14.1.1.1.1
shows the polarity of the transfer clock.
(1) When the UiC0 register's CKPOL bit = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLK
i
T D
X i
R D
X i
(2) When the UiC0 register's CKPOL bit = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
CLK
i
T D
X i
R D
X i
Note 1: This applies to the case where the UiC0 register's UFORM bit = 0
(LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).
Note 2: When not transferring, the CLKi pin outputs a high signal.
Note 3: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 14.1.1.1.1. Polarity of transfer clock

14.1.1.2 LSB First/MSB First Select Function

Use the UiC0 register (i = 0 to 2)'s UFORM bit to select the transfer format. Figure 14.1.1.2.1 shows
the transfer format.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLK
i
T D
X i
R D
X i
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLK
i
T D
X i
R D
X i
Note: This applies to the case where the UiC0 register's CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register's
UiLCH bit = 0 (no reverse).
i = 0 to 2
Figure 14.1.1.2.1 Transfer format
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
D0 D D D
1 2 3
D D D D
0 1 2 3
D D D D
0 1 2 3
D D D D
0 1 2 3
D0 D D D
1 2
D D D
D 1 2
0
D D D D
7
6 5
D D D
D 6 5
7
page 177 of 402
D D D D
4 5 6 7
D D D D
4 5 6 7
D D D D
4 5 6 7
D D D D
4 5 6 7
D D D
3 4 5 6
D D D
3 4 5 6
D D D
4 3 2 1
D D D
4 3 2 1
14.1 UARTi (i=0 to 2)
(Note 2)
(Note 3)
D
7
D
7
D
0
D
0