Renesas M16C/29 Series Hardware Manual page 185

M16C/29 Group
1SP
STPS=0
SP
RxDi
STPS=1
2SP
2SP
SP SP
1SP
Figure 14.1.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
PAR
disabled
Clock
synchronous
type
PRYE=0
SP PAR
UART
PRYE=1
enabled
0 0 0 0 0 0
PAR
STPS=1 enabled UART
PRYE=1
PAR
PRYE=0
Clock
STPS=0
synchronous
type
PAR
disabled
0
page 165 of 402
Clock
synchronous type
UART (7 bits)
UART (8 bits)
UART (7 bits)
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
0
D D D D
8 7 6 5
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D D D
D
7 6 5
8
UART (8 bits)
UART (9 bits)
Clock synchronous
UART (9 bits)
type
UART (7 bits)
UART (7 bits)
UART (8 bits)
Clock synchronous
type
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : UiMR register's bit
14.1 UARTi (i=0 to 2)
UARTi receive register
UARTi receive
D D D D D
4 3 2 1 0
buffer register
Address 03A6
Address 03A7
Address 03AE
Address 03AF
D D D D D
UARTi transmit
4 3 2 1 0
buffer register
Address 03A2
Address 03A3
Address 03AA
Address 03AB
UARTi transmit register
SP: Stop bit
PAR: Parity bit
16
16
16
16
16
16
16
16
TxDi