Renesas M16C/29 Series Hardware Manual page 226

M16C/29 Group
(1) Transmission
Transfer clock
"1"
U2C1 register
TE bit
"0"
"1"
U2C1 register
TI bit
"0"
TxD
2
Parity error signal sent
back from receiver
RxD pin level
2
(Note)
"1"
U2C0 register
TXEPT bit
"0"
"1"
S2TIC register
IR bit
"0"
The above timing diagram applies to the case where data is
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Note : Because TxD
2
sent back from receiver.
(1) Reception
Transfer clock
"1"
U2C1 register
RE bit
"0"
Transmitter's
transmit waveform
TxD
2
RxD pin level
2
(Note)
U2C0 register "1"
RI bit
"0"
S2RIC register "1"
IR bit
"0"
The above timing diagram applies to the case where data is
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Note : Because TxD
2
parity error signal received.
Figure 14.1.6.1. Transmit and Receive Timing in SIM Mode
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Tc
Start
bit
ST D D D D D
0 1 2 3 4
ST D D D D D
0 1 2 3 4
The IR bit is set to "1" at the
falling edge of transfer clock
and RxD are connected, this is composite waveform consisting of the TxD
2
Tc
Start
bit
ST
D D D D D
0 1 2 3 4
ST D D D D D
0 1 2 3 4
and RxD are connected, this is composite waveform consisting of the transmitter's transmit waveform and the
2
page 206 of 402
14.1.6 Special Mode 4 (SIM Mode) (UART2)
Write data to U2TB register
Transferred from U2TB register to UART2 transmit register
Parity Stop
bit bit
D D P ST D
D SP
7 0
5 6
An "L" level returns due to the
occurrence of a parity error.
D D D P SP ST D
5 6 7 0
The level is detected by the
interrupt routine.
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
fi : frequency of U2BRG count source (f
f : frequency of U2BRG count source (external clock)
EXT
n : value set to U2BRG
Stop
Parity
bit
bit
D ST
D D P SP D
7
5 6
An "L" level is output from TxD
the occurrence of a parity error
D D D P SP ST D
5 6 7
Read the U2RB register
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
fi : frequency of U2BRG count source (f
f : frequency of U2BRG count source (external clock)
EXT
n : value set to U2BRG
D D D D D D P
D
1 2 3 4 7
5 6
SP
D D D D D D D P
1 2 3 4 5 6 7
SP
EXT
, f
1SIO 2SIO
output and the parity error signal
2
SP
D
D D D D D D P
7
0 1 2 3 4 5 6
due to
2
D D D D D D D P
0 1 2 3 4 5 6 7
SP
EXT
, f , f
1SIO 2SIO
The level is
detected by the
interrupt routine.
, f , f )
8SIO 32SIO
Read the U2RB register
, f )
8SIO 32SIO