Renesas M16C/29 Series Hardware Manual page 191

M16C/29 Group
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Note 1: The BBS bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.).
Note 2: When a transfer begins, the SSS bit is set to "0" (Not synchronized to R
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Figure 14.1.8. Serial I/O-related registers (5)
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Symbol
U2SMR
Bit
Bit
symbol
name
2
IICM I C mode select bit
ABC Arbitration lost detecting
flag control bit
BBS Bus busy flag
Reserved bit
(b3)
Bus collision detect
ABSCS
sampling clock select bit
Auto clear function
ACSE
select bit of transmit
enable bit
Transmit start condition
SSS
select bit
Nothing is assigned. When write, set "0". When read, its content is indeterminate.
(b7)
Symbol
U2SMR2
Bit
Bit name
symbol
2
I C mode select bit 2
IICM2
CSC Clock-synchronous bit
SCL wait output bit
SWC
ALS SDA output stop bit
UART initialization bit
STAC
SWC2 SCL wait output bit 2
SDHI SDA output disable bit
Nothing is assigned. When write, set "0". When read, its content is
indeterminate.
(b7)
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Address After reset
0377 X0000000
16 2
Function
2
0 : Other than I C bus mode
2
1 : I C bus mode
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
Set to "0"
0 : Rising edge of transfer clock
1 : Underflow signal of timer A0
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
0 : Not synchronized to R D
X 2
1 : Synchronized to R D (Note 2)
X 2
Di).
X
Address After reset
0376 X0000000
16
Function
Refer to "Table 14.1.3.4. I
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0: Transfer clock
1: "L" output
0: Enabled
1: Disabled (high impedance)
14.1 UARTi (i=0 to 2)
RW
RW
RW
RW
(Note1)
RW
RW
RW
RW
2
RW
2
C bus Mode Functions"
RW
RW
RW
RW
RW
RW
RW