Renesas M16C/29 Series Hardware Manual page 95

M16C/29 Group
Priority level of each interrupt
ICOC interrupt 1, I
ICOC base timer, S
ICOC interrupt 0
UART1 reception
UART0 reception
UART2 reception, ACK2
A/D conversion, Key input interrupt
UART 2 bus collision
UART1 transmission
UART0 transmission
UART2 transmission, NACK2
CAN 0 wakeup
CAN 0 reception
CAN 0 transmission
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Voltage down detection
Figure 9.5.1.1. Interrupts Priority Select Circuit
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Level 0 (initial value)
INT1
Timer B2
Timer B0
Timer A3
Timer A1
2 C bus interface
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
/S
CL DA
DMA1
SI/O4, INT5
Timer A0
CAN 0 error
DMA0
SI/O3, INT4
IPL
I flag
DBC
NMI
page 75 of 402
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Interrupt request level resolution output to clock
generating circuit (Fig.7.1.)
9. Interrupts
Interrupt
request
accepted