Lsb First/Msb First Select Function - Renesas M16C/29 Series Hardware Manual

M16C/29 Group
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
UiC1 register
RE bit
RxDi
Transfer clock
UiC1 register
RI bit
RTSi
SiRIC register
IR bit
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 14.1.2.2. Receive Operation

14.1.2.1. LSB First/MSB First Select Function

As shown in Figure 14.1.2.1.1, use the UiC0 register's UFORM bit to select the transfer format. This
function is valid when transfer data is 8 bits long.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLK
i
T D
X i
R D
X i
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLK
i
T D
X i
R D
X i
Note: This applies to the case where the UiC0 register's CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiC1 register's UiLCH
bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and
UiMR register's PRYE bit = 1 (parity enabled).
Figure 14.1.2.1.1. Transfer Format
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
"1"
"0"
Start bit
Sampled "L"
Reception triggered when transfer clock
"1" is generated by falling edge of start bit
"0"
"H"
"L"
"1"
"0"
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program
ST D0 D
1
ST
D D
0 1
D
ST D
6
7
D
ST D
6
7
page 184 of 402
D
D
1
0
Receive data taken in
Transferred from UARTi receive
register to UiRB register
D D D D
2 3 4 5
D D D D
2 3 4 5
D D D D
5 4 3 2
D D D D
5 4 3 2
14.1 UARTi (i=0 to 2)
Stop bit
D
7
D D P SP
6 7
D D P SP
6 7
D D
P SP
1 0
D D
1 0 P SP
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2