Usage Precautions - Renesas M16C/29 Series Hardware Manual

M16C/29 Group

16.14 Usage precautions

(1) Access to the registers of I
The precaution of read/write to the control registers of I
2
•I C0 data shift register (S00 : 02E0
Do not write the register during the data transfer. The transfer bit counter is reset and the data may not be
transfered normally.
2
•I C0 control register 0 (S1D0 : address 02E3
After the start condition detection or the 1-byte transfer completion, the bit counter (bits BC2 to
BC0) is reset by Hardware. Do not read/write the register at this time, because the data may be
undetermined.
Figure 16.22 and Figure 16.23 show the bit counter reset timing by Hardware.
2
•I C0 clock control register (S20 : address 02E4
Do not write to this register except the ACKBIT during the transfer. The I
and the data may not be transfered normally.
2
•I C0 control register 1 (S3D0 : address 02E6
2
Write I C system clock select bits when I
receive completion interrupt enable bit (WIT) reads out, the internal WAIT flag is read.Do not use the
bit managing instrustion (read-modify-write instruction) to access the register.
2
•I C0 status register (S10 : address 02E8
Do not use the bit managing instruction (read-modify-write instruction) to access the register be
cause all bits of this register are changed by H/W. Do not read/write during the timing when the MST
and the TRX bits for the communication mode setting are changed. The data may be undetermined.
Figure16.21 to Figure 16.23 show the timing when the MST and the TRX bits are changed by H/W.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
2
C bus interface circuit
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16
page 277 of 402
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C bus interface circuit is as follows.
).
16
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16
)
16
2
C bus interface enable bit (ES0)is disabled. When the data
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16
2
16. MULTI-MASTER I C bus INTERFACE
2
C clock generator is reset