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M16C/29 Group
16.12 START/STOP Condition Detect Operation
Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. The START/
STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected
only when the input signal of the S
setup time, and the hold time (see Table.16.10 Start/Stop condition detect conditions). The BB flag is
set to "1" by detecting the start condition and is set to "0" by detecting the stop condition. The BB flag set
and reset timing are different in standard clock mode and high-speed clock mode. See Table.16.10 Start/
Stop condition detect conditions.
S
CL
S
DA
BB flag
Figure 16.18 Start condition detection timing diagram
S
CL
S
DA
BB flag
Figure 16.19 Stop condition detection timing diagram
Table 16.10 Start/Stop detection timing table
S
release time
CL
Setup time
Hold time
BB flag set/reset
time
Note 1. Unit : Cycle numbers of I
The SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0.
Do not set "0" or odd numbers to the SSC value. The values in () are examples when the I
start/stop condition control register is set to "18
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
and S
CL
S
release time
CL
Setup
Hold
time
time
BB flag
set time
S
release time
CL
Setup
Hold
time
time
BB flag
reset time
Standard clock mode
SSC value + 1 cycle (6.25µs)
SSC value + 1 cycle < 4.0µs (3.25µs)
2
SSC value
cycle < 4.0µs (3.0µs)
2
SSC value - 1 +2 cycles (3.375µs)
2
2
C system clock V
page 273 of 402
pins satisfied with three conditions: the S
DA
IIC
" at V
= 4 MHz.
16
IIC
2
16. MULTI-MASTER I
C bus INTERFACE
release time, the
CL
High-speed clock mode
4 cycles (1.0µs)
2 cycles (0.5µs)
2 cycles (0.5µs)
3.5 cycles (0.875µs)
2
C0
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