Renesas M16C/29 Series Hardware Manual page 273

M16C/29 Group
2
I C0 control register 1
b7 b6 b5 b4 b3 b2
Note 1: Effective when ES0 bit in S1D0 register is "1"(I
Note 2: When PCLK0 bit in PCLKR register is "0", f
2
Figure 16.6 I C0 control register 1
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b1 b0
Symbol
S3D0
Bit Symbol
SIM The interrupt enable bit for
STOP condition detection
WIT The interrupt enable bit for
data receive completion
S /Port function switch
DAi
PED
bit
S /Port function switch
CLi
PEC
bit
The logic value monitor
SDAM
bit of S
The logic value monitor
SCLM
bit of S
2
ICK0
I C system clock
selection bits,
if ICK4 to ICK2 bits in the
ICK1
S4D0 register is "000
page 253 of 402
16. MULTI-MASTER I
Address
02E6
16
Bit Name
0: Disable the I
interrupt of STOP condition
detection
1: Enable the I
interrupt of STOP condition
detection
0: Disable the I
interrupt of data receive
completion
1: Enable the I
interrupt of data receive
completion
When setting NACK
(ACK bit = 0), write "0"
0: S
DA
1: Port output pin (enable ES0 = 1)
(Note 1)
0: S
CL
1: Port output pin (enable ES0 = 1)
(Note 1)
0: S
DA
output 1: S
DA DA
0: S
CL
output 1: S
CL
CL
b7 b6
0 0 :
0 1 :
1 0 :
"
2
1 1 : Reserved
2
C bus interface enable).
is f . When PCLK0 bit is "1", f
IIC 2
2
C bus INTERFACE
When reset
00110000
2
Function
2
C bus interface
2
C bus interface
2
C bus interface
2
C bus interface
I/O pin (enable ES0 = 1)
I/O pin (enable ES0 = 1)
output logic value = 0
output logic value = 1
output logic value = 0
output logic value = 1
=1/2 f
V
IIC
IIC
V =1/4f
IIC IIC
=1/8f
V
IIC IIC
(Note 2)
is f .
IIC 1
RW
RW
RW
RW
RW
RO
RO
RW
RW