Renesas M16C/29 Series Hardware Manual page 196

M16C/29 Group
(1) Example of transmit timing
Transfer clock
"1"
UiC1 register
"0"
TE bit
"1"
UiC1 register
TI bit
"0"
"H"
CTSi
"L"
CLKi
TxDi
"1"
UiC0 register
TXEPT bit
"0"
SiTIC register "1"
IR bit
"0"
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register CKDIR bit = 0 (internal clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
(2) Example of receive timing
"1"
UiC1 register
"0"
RE bit
"1"
UiC1 register
"0"
TE bit
"1"
UiC1 register
TI bit
"0"
"H"
RTSi
"L"
CLKi
RxDi
"1"
UiC1 register
RI bit
"0"
"1"
SiRIC register
IR bit
"0"
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register CKDIR bit = 1 (external clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive
Figure 14.1.1.1. Typical transmit/receive timings in clock synchronous serial I/O mode
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Tc
Write data to the UiTB register
Transferred from UiTB register to UARTi transmit register
T
CLK
D D D
D D D D D
0 1 2 3 4 5 6
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program
Write dummy data to UiTB register
Transferred from UiTB register to UARTi transmit register
1 / f
EXT
Receive data is taken in
D
D D D D D D
0 1 2 3 4 5 6
Transferred from UARTi receive register
to UiRB register
Cleared to "0" when interrupt request is
accepted, or cleared to "0" in a program
data taken in at the rising edge of the transfer clock)
page 176 of 402
Stopped pulsing because CTSi = "H"
D D D
D D D D D
7 7
0 1 2 3 4 5 6
Tc = T = 2(n + 1) / fj
CLK
fj: frequency of UiBRG count source (f
n: value set to UiBRG register
i: 0 to 2
register bit 1, and U2IRS bit is the U2C1 register bit 4
Even if the reception is completed, the RTS
does not change. The RTS becomes "L"
when the RI bit changes to "0" from "1".
D D D D D D D
7 0 1 2 3 4 5
Read out from UiRB register
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
• UiC0 register TE bit = 1 (transmit enabled)
• UiC0 register RE bit = 1 (Receive enabled)
• Write dummy data to the UiTB register
14.1 UARTi (i=0 to 2)
Stopped pulsing because the TE bit = "0"
D D D
D D D D D
7
0 1 2 3 4 5 6
, f , f , f
1SIO 2SIO 8SIO 32SIO
)