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M16C/29 Group
13.5.2 Phase-Delayed Waveform Output Mode
Output level of the OUTC1j pin is inverted whenever the value of the base timer matches that of the
G1POj register value ( j=0 to 7). Table 13.5.2.1 lists specifications of phase-delayed waveform mode.
Figure 13.5.2.1 lists an example of phase-delayed waveform mode operation.
Table 13.5.2.1. Phase-delayed Waveform Output Mode Specifications
Item
Output waveform
Waveform output start condition(Note 1) The IFEj bit in the G1FE register should be set to "1" (channel j function enabled)
Waveform output stop condition
Interrupt request
OUTC1j pin(Note 2)
Selectable function
Note 1 : The FSCj bit in the G1FS register should be set to "0" (waveform generation function selected) in the channels
shared by the time measurement function and waveform generation function.
Note 2 : The OUTC1
0
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
• Free-running operation
(the RST1, RST2, and RST4 bits of the G1BCR1 and G1BCR0 registers are set
to "0" (no reset))
Cycle
"H" and "L" width
• Setting bit RST1 to "1", and bits RST4 and RST2 to "0" enables the base
timer to be reset when its value matches the G1PO0 register. Likewise,
setting bit RST4 to "1",and bits RST2 and RST1 to "0" enables the base timer
to be reset when its value matches the G1BTRR register.
Cycle
"H" and "L" width
n : setting value of either G1PO0 register or G1BTRR register, 0001
The IFEj bit should be set to "0" (channel j function disabled)
The G1IRj bit in the interrupt request register is set to "1" when value of the
base timer matches one of the G1POj registers. (See Figure 13.10.)
Pulse output
• Default value set function : Output level is set when waveform output starts
• Inverse output function : Waveform level is inverted to output waveform from
the OUTC1j pin
to OUTC1
pins.
7
page 157 of 402
13. Timer S (Input Capture / Output Compare)
Specification
65536 x 2
:
f
BT1
65536
:
f
BT1
2(n+2)
:
f
BT1
n+2
:
f
BT1
to FFFD
16
16
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