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M16C/29 Group
14.1.4 Special Mode 2 (UART2)
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 14.1.4.1 lists the specifications of Special Mode 2. Table 14.1.4.2 lists the registers
used in Special Mode 2 and the register values set. Figure 14.1.4.1 shows communication control ex-
ample for Special Mode 2.
Table 14.1.4.1. Special Mode 2 Specifications
Item
Transfer data format
Transfer clock
Transmit/receive control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
Note 1: When an external clock is selected, the conditions must be met while if the U2C0 register's CKPOL bit = "0"
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the U2C0 register's CKPOL bit = "1" (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low
state.
Note 2: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC register does
not change.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
• Transfer data length: 8 bits
• Master mode
U2MR register's CKDIR bit = "0" (internal clock) : fj/ 2(n+1)
fj = f
, f
1SIO
2SIO
• Slave mode
CKDIR bit = "1" (external clock selected) : Input from CLK2 pin
Controlled by input/output ports
• Before transmission can start, the following requirements must be met (Note 1)
_
The TE bit of U2C1 register= 1 (transmission enabled)
_
The TI bit of U2C1 register = 0 (data present in U2TB register)
• Before reception can start, the following requirements must be met (Note 1)
_
The RE bit of U2C1 register= 1 (reception enabled)
_
The TE bit of U2C1 register= 1 (transmission enabled)
_
The TI bit of U2C1 register= 0 (data present in the U2TB register)
• For transmission, one of the following conditions can be selected
_
The U2IRS bit of U2C1 register = 0 (transmit buffer empty): when transferring data
from the U2TB register to the UART2 transmit register (at start of transmission)
_
The U2IRS bit =1 (transfer completed): when the serial I/O finished sending data
from the UART2 transmit register
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 7th bit of the next data
• Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
page 197 of 402
Specification
, f
, f
. n: Setting value of U2BRG register
8SIO
32SIO
14.1.4 Special Mode 2 (UART2)
00
to FF
16
16
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