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M16C/29 Group
(2) Generation of RESTART condition
After 1-byte data transfer and a restart condition is generated, write"E0
start condition standby and the S
ates the start condition trigger after waiting in software until the S
the restart condition generation timing.
8 clock
S
CL
S
DA
S1I writing signal
( START condition setting standby)
S0I writing signal
(START condition trigger generation)
Figure 16.24 The time of generation of RESTART condition
(3) Iimitation of CPU clock
The registers of I
to the sub clock (X
0006h, CM07 bit). Select the main clock (X
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
pin will be released. Writing to the I
DA
ACK
clock
2
C bus interface circuit can not be read from or written to if the CPU clock is selected
, X
) by the system clock select bit (system clock control register 0, address
CIN
COUT
page 279 of 402
16. MULTI-MASTER I
DA
Insert software wait
, X
) or the on-chip oscillator clock in read/write.
IN
OUT
2
C bus INTERFACE
2
" to I
C0 status register, set the
16
2
C0 data shift register gener-
becomes "H". Figure 16.24 shows
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