I 2 C0 Control Register 2 (S3D0 Register) - Renesas M16C/29 Series Hardware Manual

M16C/29 Group
2
16.7 I C0 control register 2 (S3D0 register)
2
I C0 control register 2 (address: 02E7
communication, the data transfer is controlled by the S
nication state if the S
state for a period of time, the I
2
I C bus interface interrupt request. Please see Figure 16.13 The timing of time out detection.
BB flag
Internal counter start signal
Internal counter stop, reset signal
Internal counter overflow signal
2
I C bus interface interrupt
request signal
Figure 16.13 The timing of time out detection
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
16
clock is stopped during the transfer. To avoid that, if the S
CL
2
C bus interface circuit has the function to detect the time out and generate an
1 clock
S
CL
1 bit
S
DA
page 267 of 402
) controls the abnormal communication detection. In the I
clock signal. The devices are stoped in the commu-
CL
2 clock
2 bit 3 bit
2
16. MULTI-MASTER I C bus INTERFACE
clock is stopped in "H"
CL
S clock stop ("H")
CL
3 clock
The time of timeout detection
2
C bus