Renesas M16C/29 Series Hardware Manual page 105

M16C/29 Group
DMA0 request cause select register
b7 b6
Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request)
0 0 0 0
2
0 0 0 1
2
0 0 1 0
2
0 0 1 1
2
0 1 0 0
2
0 1 0 1
2
0 1 1 0
2
0 1 1 1
2
1 0 0 0
2
1 0 0 1
2
1 0 1 0
2
1 0 1 1
2
1 1 0 0
2
1 1 0 1
2
1 1 1 0
2
1 1 1 1
2
Figure 11.2 DM0SL Register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Symbol
b5 b4 b3 b2 b1 b0
DM0SL
Bit symbol
DSEL0
DSEL1
DSEL2
DSEL3
(b5-b4)
DMS
DSR
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
A/D conversion
UART1 transmit
page 85 of 402
Address
03B8
16
Bit name
DMA request cause Refer to note
select bit
Nothing is assigned. When write, set to "0".
When read, its content is "0".
DMA request cause
0: Basic cause of request
expansion select bit
1: Extended cause of request
A DMA request is generated by
Software DMA
setting this bit to "1" when the DMS
request bit
bit is "0" (basic cause) and the
DSEL3 to DSEL0 bits are "0001
(software trigger).
The value of this bit when read is "0" .
DMS=1(extended cause of request)
ICOC base timer
–
ICOC channel 0
ICOC channel 1
–
–
Two edges of INT0 pin
–
–
–
ICOC channel 2
ICOC channel 3
ICOC channel 4
ICOC channel 5
ICOC channel 6
ICOC channel 7
After reset
00
16
Function
RW
RW
RW
RW
RW
RW
RW
"
2
11. DMAC