Renesas M16C/29 Series Hardware Manual page 11

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16.4.5 Bit 7: I
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16.5 I C0 Status Register (S10 register) ........................................................................... 261
16.5.1 Bit 0: Last receive bit (LRB) ................................................................................ 261
16.5.2 Bit 1: General call detection flag (ADR0) ............................................................ 261
16.5.3 Bit 2: Slave address comparison flag (AAS) ....................................................... 261
16.5.4 Bit 3: Arbitration lost detection flag (AL)(Note 1) ................................................. 261
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16.5.5 Bit 4: I
16.5.6 Bit 5: Bus busy flag (BB) ..................................................................................... 262
16.5.7 Bit 6: Communication mode select bit (transfer direction select bit: TRX) .......... 263
16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) ............... 263
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16.6 I C0 control register 1 (S3D0 register) ...................................................................... 264
16.6.1 Bit 0 : Interrupt enable bit by STOP condition (SIM ) .......................................... 264
16.6.2 Bit 1: Interrupt enable bit at the completion of data receive (WIT) ...................... 264
16.6.3 Bits 2,3 : Port function select bits PED, PEC ...................................................... 265
16.6.4 Bits 4,5 : SDA/SCL logic output value monitor bits SDAM/SCLM ....................... 266
16.6.5 Bits 6,7 : I
16.6.6 The address receive in STOP mode/WAIT mode ............................................... 266
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16.7 I C0 control register 2 (S3D0 register) ....................................................................... 267
16.7.1 Bit0: Time out detection function enable bit (TOE) .............................................. 268
16.7.2 Bit1: Time out detection flag (TOF ) .................................................................... 268
16.7.3 Bit2: time out detection period select bit (TOSEL) .............................................. 268
16.7.4 Bits 3,4,5: I
16.7.5 Bit7: STOP condition detection interrupt request bit (SCPIN) ............................. 268
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16.8 I C0 START/STOP condition control registers (S2D0 register) ................................. 269
16.8.1 Bit0-Bit4: START/STOP condition setting bits (SSC0-SSC4) ............................. 269
16.8.2 Bit5: SCL/SDA interrupt pin polarity select bit (SIP) ............................................ 269
16.8.3 Bit6 : SCL/SDA interrupt pin select bit (SIS) ....................................................... 269
16.8.4 Bit7: START/STOP condition generation select bit (STSPSEL) .......................... 269
16.9 START Condition Generation Method ....................................................................... 270
16.10 START condition duplicate protect function .............................................................. 271
16.11 STOP Condition Generation Method ........................................................................ 271
16.12 START/STOP Condition Detect Operation ............................................................... 273
16.13 Address Data Communication ................................................................................. 274
16.13.1 Example of Master Transmit ............................................................................. 274
16.13.2 Example of Slave Receive ................................................................................ 275
16.14 Usage precautions .................................................................................................... 277
17. CAN Module ...............................................................................................280
17.1. CAN Module-Related Registers ................................................................................ 281
C bus interface pin input level select bit (TISS) ....................................... 260
C bus interface interrupt request bit (PIN) ............................................... 262
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C system clock select bits ICK0, ICK1 ............................................... 266
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C system clock select bits (ICK2-4) ................................................. 268
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