Timer B - Renesas M16C/29 Series Hardware Manual

M16C/29 Group

12.2 Timer B

Figure 12.2.1 shows a block diagram of the timer B. Figures 12.2.2 and 12.2.3 show registers related to the
timer B.
Timer B supports the following four modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 2)
to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
• A/D trigger mode: The timer counts only once before it reaches the minimum count "0000
Clock source selection
f or f
1 2
f
8
f
32
f
C32
Polarity switching,
TBi
IN
edge pulse
(i = 0 to 2)
Can be selected in only
event counter mode
TBj overflow (Note)
(j = i – 1, except j = 2 if i = 0)
Note: Overflow or underflow.
Figure 12.2.1. Timer B Block Diagram
Timer Bi mode register (i=0 to 2)
b7 b6 b5 b4 b3
Note 1: Timer B0.
Note 2: Timer B1, Timer B2.
Figure 12.2.2. TB0MR to TB2MR Registers
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
• Timer
• Pulse period measuremnet,
pulse width measurement
• Event counter
Symbol
b2 b1 b0
TB0MR to TB2MR
Bit symbol
TMOD0
Operation mode select bit
TMOD1
MR0
MR1
MR2
MR3
TCK0
Count source select bit
TCK1
page 109 of 402
Data bus high-order bits
Clock selection
TABSR register
Counter reset circuit
TBi
Timer B0
Timer B1
Timer B2
Address After reset
039B to 039D 00XX0000
16 16
Bit
name
b1 b0
0 0 : Timer mode or A/D trigger mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
Function varies with each operation
mode
Function varies with each operation
mode
Data bus low-order bits
High-order 8 bits
Low-order 8 bits
Reload register
Counter
Address TBj
0391 0390 Timer B2
-
16 16
0393 0392 Timer B0
-
16 16
0395 0394 Timer B1
-
16 16
2
Function
(Note 1)
(Note 2)
12.2 Timer B
"
16
RW
RW
RW
RW
RW
RW
RO
RW
RW