Renesas M16C/29 Series Hardware Manual page 270

M16C/29 Group
2
I C0 data shift register
b7 b6 b5 b4 b3
2
I C0 clock control register
b7 b6 b5 b4 b3 b2
2
Figure 16.3 I C0 data shift register, I
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Symbol
b2 b1 b0
S00
Transmit/receive data are stored.
In the master transmit mode, the start condition/stop condition are triggered
by writing data to the register (refer to Section 16.9 START Condition
Generation Method and Section16.11 STOP Condition Generation
Method). The transmit/receive are started synchronized with S
Note 1: The write is only enabled when the bus interface enable bit (ES0 bit) is "1".
Because the register is used both for storing transmit/receive data, Write the
transmit data after the receive data is read out when transmitting.
b1 b0
Symbol
S20
Bit Symbol
S frequency control bits
CL
CCR0
CCR1
CCR2
CCR3
CCR4
FAST
S
CL
MODE
ACK BIT ACK bit
ACK ACK clock bit
2
C0 clock control register
page 250 of 402
Address
02E0
16
Function
Address
02E4
16
Bit Name
mode specification bit
2
16. MULTI-MASTER I
When reset
XX
16
.
CL
After reset
00
16
Function
See table 16.3 Set values
2
of I C0 clock control
register and S
CL
frequency
0: Standard clock mode
1: High-speed clock mode
0: ACK is returned
1: ACK is not returned
0: No ACK clock
1: With ACK clock
C bus INTERFACE
RW
RW
(Note 1)
RW
RW
RW
RW
RW
RW
RW
RW
RW