Renesas M16C/29 Series Hardware Manual page 298

M16C/29 Group
S
CL
S
DA
BB flag
Bit reset signal
Related bits
Figure 16.21 The bit reset timing (The STOP condition detection)
S
CL
S
DA
BB flag
Bit reset signal
Related bits
BC0 - BC2
TRX(slave mode)
Figure 16.22 The bit reset timing (The START condition detection)
S
CL
PIN bit
Bit reset signal
Bit set signal
Figure 16.23 Bit set/reset timing ( at the completion of data transfer)
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
MST
TRX
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16. MULTI-MASTER I
1.5V cycle
IIC
The bits referring
2V cycle
IIC
The bits referring
1V cycle
IIC
2
C bus INTERFACE
BC0 - BC2
MST(When in arbitration lost)
to reset
TRX(When in NACK receive in slave
transmit mode)
TRX(ALS=0 meanwhile the slave
to set
receive R/W bit = 1