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M16C/29 Group
Voltage Down Detection Circuit
VC27
VCC
+
Noise
Rejection
VREF
-
(Rejection Range:200 ns)
The Voltage down detection
signal becomes "H" when the
VC27 bit is set to "0" (disabled)
WAIT instruction(wait mode)
Watchdog Timer Block
Watchdog timer
underflow signal
Figure 5.5.1.1 Power Supply Down Detection Interrupt Generation Block
VCC
VC13 bit in VCR1 register
(2)
Output of the digital filter
D42 bit in D4INT register
Voltage down detection
interrupt signal
NOTES :
1. D40 bit in the D4INT register is set to "1" (voltage down detection interrupt enabled).
2. Output of the digital filter is shown in Figure 6.5.
Figure 5.5.1.2 Power Supply Down Detection Interrupt Generation Circuit Operation Example
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Voltage down detection interrupt generation circuit
D4INT clock(the
1/8
1/2
clock with which it
operates also in
wait mode)
VC13
Voltage down
detection signal
CM10
CM02
D43
This bit is set to "0"(not detected) by program.
sampling
page 35 of 402
DF1, DF0
00b
The D42 bit is set to "0" (not detected)
01b
by program. the VC27 bit is set to "0"
(voltage down detect circuit disabled),
10b
the D42 bit is set to "0".
11b
1/2
1/2
D42
Noise Rejection
Digital
Circuit
Filter
D41
sampling
No voltage down detection interrupt signals are
generated when the D42 bit is "H".
Set to "0" by program (not detected)
Watchdog
timer interrupt
signal
Voltage down
detection
interrupt signal
Oscillation stop,
re-oscillation
detection
interrupt signal
D40
sampling
sampling
5. Reset
Non-maskable
interrupt signal
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