Clock Generation Circuit - Renesas M16C/29 Series Hardware Manual

M16C/29 Group

7. Clock Generation Circuit

The clock generation circuit contains four oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
(3) Variable on-chip oscillator (available at reset, oscillation stop detect function)
(4) PLL frequency synthesizer
Table 7.1 lists the clock generation circuit specifications. Figure 7.1 shows the clock generation circuit.
Figures 7.2 to 7.6 show the clock-related registers.
Table 7.1. Clock Generation Circuit Specifications
Item
oscillation circuit
CPU clock source
Use of clock
Peripheral function
clock source
Clock frequency 0 to 20 MHz
Ceramic oscillator
Usable oscillator
Crystal oscillator
X
Pins to connect
IN
oscillator
Available
Oscillation stop,
restart function
Oscillating
Oscillator status
after reset
Externally derived clock can be input
Other
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Main clock
Sub clock
oscillation circuit
CPU clock source
Timer A, B's clock
source
32.768 kHz
Crystal oscillator
, X X , X
OUT CIN COUT
Available
Stopped
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Variable on-chip oscillator
CPU clock source
Peripheral function clock source
CPU and peripheral function
clock sources when the main
clock stops oscillating
Selectable source frequency:
f , f , f
1(ROC) 2(ROC) 3(ROC)
Selectable divider:
by 2, by 4, by 8
Available
Oscillating
(CPU clock source)
7. Clock Generation Circuit
PLL frequency
synthesizer
CPU clock source
Peripheral function clock
source
10 to 20 MHz
Available
Stopped