Arbitration - Renesas M16C/29 Series Hardware Manual

M16C/29 Group
Table 14.1.3.2.1. STSPSEL Bit Functions
Function
Output of SCL2 and SDA2 pins
Start/stop condition interrupt
request generation timing
(1) When slave
CKDIR="1" (external clock)
STPSEL bit (= "0")
SCL2
SDA2
(2) When master
CKDIR="0" (internal clock), CKPH="1" (clock delayed)
STPSEL bit
SCL2
SDA2
Figure 14.1.3.2.1. STSPSEL Bit Functions

14.1.3.3 Arbitration

Unmatching of the transmit data and SDA
edge of SCL
2
ABT bit is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to "1" at the same time
unmatching is detected during check, and is cleared to "0" when not detected. In cases when the ABC
bit is set to "1", if unmatching is detected even once during check, the ABT bit is set to "1" (unmatching
detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise,
clear the ABT bit to "0" (undetected) after detecting acknowledge in the first byte, before transferring
the next byte.
Setting the U2SMR2 register's ALS bit to "1" (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDA
is set to "1" (unmatching detected).
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
STSPSEL = 0
Output of transfer clock and
data
Output of start/stop condition is
accomplished by a program
using ports (not automatically
generated in hardware)
Start/stop condition detection
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
Start condition
detection interrupt
Set to "1" in Set to "0" in
a program a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
Set STAREQ=
"1" (start)
Start condition
detection interrupt
. Use the U2SMR register's ABC bit to select the timing at which the U2RB register's
pin is placed in the high-impedance state at the same time the ABT bit
2
page 194 of 402
14.1.3 Special Mode 1 (I
STSPSEL = 1
Output of a start/stop condition
according to the STAREQ,
RSTAREQ and STPREQ bit
Finish generating start/stop condi-
tion
Stop condition
detection interrupt
Set to "1" in
a program
Set STPREQ=
"1" (start)
pin input data is checked synchronously with the rising
2
2
C bus mode) (UART2)
Set to "0" in
a program
Stop condition
detection interrupt