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M16C/29 Group
1.10 Precautions for A/D Converter
1. Set ADCON0 (except bit 6), ADCON1, ADCON2 and ADTRGCON registers when A/D conversion is
stopped (before a trigger occurs).
2. When the VCUT bit of ADCON1 register is changed from "0" (Vref not connected) to "1" (Vref con-
nected), start A/D conversion after passing 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AV
AV
pin. Similarly, insert a capacitor between the V
SS
connection of each pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to "0" (input
mode). Also, if the ADCON0 register's TGR bit = 1 (external trigger), make sure the port direction bit for
___________
the AD
pin is set to "0" (input mode).
TRG
5. When using key input interrupts, do not use any of the four AN
input interrupt request is generated when the A/D input voltage goes low.)
6. The φ
frequency must be 10 MHz or less. Without sample-and-hold function, limit the φ
AD
or more. With the sample and hold function, limit the φ
to 250kH
Z
7. When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits of
ADCON0 register and the SCAN1 to SCAN0 bits of ADCON1 register.
C4
AN
: AN
i
NOTES
1. C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Figure 1.10.1. Use of capacitors to reduce noise
Rev.1.00 Nov 01,2004
REJXXXXXXX-0100Z
, V
, and analog input pins (AN
CC
REF
Microcomputer
AV
CC
V
REF
AV
SS
V
CC
AN
V
SS
(i=0 to 7), AN
(i=0 to 7 for 80-pin version, and i=0 to 3 for 64-pin version)
i
0i
AN
(i=0 to 7 for 80-pin version, i=4 for 64-pin version), AN
2i
page 22 of 31
pin and the V
CC
C2
C1
C3
i
, AN
, AN
(i=0 to 7)) each and the
i
0i
2i
pin. Figure 1.10.1 is an example
SS
to AN
pins as analog inputs. (A key
4
7
frequency to 1MH
AD
Z
(i=0 to 2)
3i
frequency
AD
or more.
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