Renesas M16C/29 Series Hardware Manual page 134

M16C/29 Group
Count source
Measurement pulse
Reload register
transfer timing
Timing at which counter
reaches "0000 "
16
TBiS bit
TBiIC register's
IR bit
TBiMR register's
MR3 bit
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7.
i = 0 to 2
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are "00
from falling edge to falling edge of the measurement pulse).
Figure 12.2.3.2 Operation timing when measuring a pulse period
Count source
Measurement pulse
Reload register
transfer timing
Timing at which counter
reaches "0000 "
16
TBiS bit
TBiIC register's
IR bit
TBiMR register's
MR3 bit
i = 0 to 2
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are "10
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
Figure 12.2.3.3 Operation timing when measuring a pulse width
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
"H"
"L"
counter
"1"
"0"
"1"
"0"
Set to "0" upon accepting an interrupt request or by writing in
program
"1"
"0"
"H"
"L"
counter
"1"
"0"
"1"
"0"
Set to "0" upon accepting an interrupt request or by
"1" writing in program
"0"
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7.
page 114 of 402
Transfer
(indeterminate value)
(Note 1)
Transfer
Transfer Transfer
(measured value)
(indeterminate (measured
value) value)
(Note 1) (Note 1)
Transfer
(measured value)
(Note 1)
" (measure the interval
2
Transfer
(measured value)
(Note 1) (Note 1) (Note 2)
" (measure the interval
2
12.2 Timer B
(Note 2)