Renesas M16C/29 Series Hardware Manual page 154

M16C/29 Group
Figures 13.2 to 13.11 show registers associated with the IC/OC base timer, the time measurement function,
and the waveform generation function.
Base timer register
b15 b8
(b7) (b0)
Note 1: The value which is written in this register is updated synchronously with the base timer count source f
Note 2: This base timer stops only when the BCK1 to BCK0 bits in the G1BCR0 register are set to "00
source clock stop). This base timer operates when the BCK1 to BCK0 bits are set to other than "00
When the BTS bit in the G1BCR1 register is set to "0", the base timer continues to be held in reset, and
remains in a no counting state with a value of "0000
set to "1", this state is cleared and the timer starts counting.
Base timer control register 0
b7 b6 b5 b4
0 0
Note 1: This setting can be used when the UD1 to UD0 bits in the G1BCR1 register are set to "10
phase signal processing mode). Avoid setting the BCK1 to BCK0 bits to "10
Note 2: When the PCLK0 bit in the PCLKR register is "1", the selected clock source is f1. When the
PCLK0 bit is "0", the selected clock source is f2.
Figure 13.2. G1BT and G1BCR0 Registers
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
(Note 1)
b7 b0
Symbol
G1BT
When the base timer is operating:
When read, value of the counter can be read.
When write, the counter starts counting from the
value written. When the base timer is reset, this
register is set to "0000
When the base timer is reset:
This register is set to "0000
is indeterminate. No value is written. (Note 2)
b3 b2 b1 b0
Symbol
0
G1BCR0
Bit
symbol
BCK0
BCK1
RST4
(b5-b3)
CH7INSEL
IT
page 134 of 402
13. Timer S (Input Capture / Output Compare)
Address
0321 - 0320
16 16
Function
". (Note 2)
16
" but a value read
16
". When the BTS bit in the G1BCR1 register is
16
Address
0322
16
Bit name
b1 b0
0 0
: Clock stop
Count source
0 1
: Avoid this setting
select bit
1 0
: Two-phase input (Note 1)
1 1
: f or f
1
0: Base timer not reset by matching
Base timer reset
G1BTRR
cause select bit 4
1: Base timer reset by matching
G1BTRR
Reserved bit Should be set to 0"
Channel 7 Input 0: P2 /OUTC1
7
select bit 1: P1 /INT5/INPC1
7
Base timer 0: Bit 15 overflow
overflow select bit 1: Bit 14 overflow
When reset
????
16
Setting range
0000 to FFFF
16 16
" (count
2
When reset
0000 0000
2
Function
(Note 2)
2
/INPC1 pin
7 7
/IDU pin
7
" (two-
2
" in other modes.
2
RW
RW
.
BT1
".
2
RW
RW
RW
RW
RW
RW
RW