Renesas M16C/29 Series Hardware Manual page 212

M16C/29 Group
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
SCL2
SDA2
(2) IICM2= 0, CKPH= 1 (clock delay)
SCL2
SDA2
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
SCL2
SDA2
(4) IICM2= 1, CKPH= 1
SCL2
SDA2
This diagram applies to the case where the following condition is met.
• U2MR register CKDIR bit = 0 (Slave selected)
Figure 14.1.3.2. Transfer to U2RB Register and Interrupt Timing
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
1st bit 2nd bit 3rd bit 4th bit 5th bit
D7
D D D
6 5 4
1st bit 2nd bit 3rd bit 4th bit
D7
D D D
6 5 4
1st bit 2nd bit 3rd bit 4th bit 5th bit
D D D
D7 6 5 4
1st bit 2nd bit 3rd bit 4th bit
D7
D D D
6 5 4
b15
•••
page 192 of 402
14.1.3 Special Mode 1 (I
6th bit 7th bit 8th bit 9th bit
D D D D
3 2 1 0
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to U2RB register
5th bit 6th bit 7th bit 8th bit 9th bit
D D D D
3 2 1 0
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to U2RB register
6th bit 7th bit 8th bit 9th bit
D D D D
3 2 1 0
Receive interrupt
(DMA1 request)
Transfer to U2RB register
5th bit 6th bit 7th bit 8th bit 9th bit
D D D D
3 2 1 0
Receive interrupt
(DMA1 request)
Transfer to U2RB register
b9 b8 b7 b0
D0 D7 D6 D5 D4 D3 D2 D1
U2RB register
2
C bus mode) (UART2)
D (ACK, NACK)
8
b15 b9 b8 b7
D8 D7 D6 D5 D4 D3 D2 D1
•••
U2RB register
D (ACK, NACK)
8
b15 b9 b8 b7
D8 D7 D6 D5 D4 D3 D2 D1
•••
U2RB register
D (ACK, NACK)
8
Transmit interrupt
b15 b9 b8 b7
D0 D7 D6 D5 D4 D3 D2
•••
U2RB register
D (ACK, NACK)
8
Transmit interrupt
Transfer to U2RB register
b15 b9 b8 b7
D8 D7 D6 D5 D4 D3 D2 D1 D0
•••
U2RB register
b0
D0
b0
D0
b0
D1
b0