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M16C/29 Group
ROM code protect control address
b7
b6
b5
b4
b3
1
Note 1: When the ROMCR bits are set to other than '00
'11
' (ROM code protect enabled), the flash memory is disabled against reading and rewriting in
2
parallel input/output mode.
Note 2: When the ROMCR bits are set to '00
ROMCR bits can not be modified in parallel input/output mode, modify in standard serial input/
output mode.
Note 3: The ROMCP1 bits are valid when the ROMCR bits are '01
Note 4: This bit can not be set to "1" once it is set to "0". The ROMCP register is set to 'FF
block, including the ROMCP register, is erased.
Figure 21.3.1.1. ROMCP Register
Figure 21.3.2.1. Address for ID Code Stored
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Symbol
b2
b1
b0
ROMCP
1
1
1
Bit symbol
Reserved bit
Reserved bit
Reserved bit
Reserved bit
ROM code protect reset
ROMCR
bit (Note 2, Note 4)
ROM code protect level
ROMCP1
1 set bit
(Note 1, Note 3, Note 4)
Address
0FFFDF
to 0FFFDC
16
16
0FFFE3
to 0FFFE0
16
16
0FFFE7
to 0FFFE4
16
16
0FFFEB
to 0FFFE8
16
16
0FFFEF
to 0FFFEC
16
16
0FFFF3
to 0FFFF0
16
16
0FFFF7
to 0FFFF4
16
16
0FFFFB
to 0FFFF8
16
16
0FFFFF
to 0FFFFC
16
16
page 371 of 402
Address
Factory Setting
0FFFFF
FF
(Note 4)
16
16
Bit name
Set this bit to "1"
Set this bit to "1"
Set this bit to "1"
Set this bit to "1"
b5 b4
00: Disables protect
01:
10:
11:
b7 b6
00:
01:
10:
11: Disables protect
' and the ROMCP1 bits are set to other than
2
', the ROM code protect level 1 is reset. Because the
2
', '10
2
ID1
Undefined instruction vector
ID2
Overflow vector
BRK instruction vector
ID3
Address match vector
ID4
Single step vector
ID5
Watchdog timer vector
ID6
DBC vector
ID7
NMI vector
Reset vector
ROMCP
4 bytes
21. Flash Memory Version
Function
}
Enables ROOMCP1 bit
}
Enables protect
' or '11
'.
2
2
' when a
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
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