Renesas M16C/29 Series Hardware Manual page 62

M16C/29 Group
Oscillation stop detection register (Note 1)
b7 b6 b5 b4 b3
0 0
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: If CM20 bit is "1", CM27 bit is "1", the CPU clock source is the main clock, and the main clock stop is
detected, then the CM21 bit is automatically set to "1".
Note 3: If the CM20 bit is "1" and the CM23 bit is "1" (main clock not oscillating), do not set the CM21 bit to "0".
Note 4: This flag is set to "1" when the main clock is detected to have stopped or when the main clock is
detected to have restarted oscillating. When this flag changes state from "0" to "1", an oscillation stop,
re-oscillation detection interrupt is generated. Use this flag in an interrupt routine to discriminate the
causes of interrupts between the oscillation stop, re-oscillation detection interrupts and the watchdog
timer interrupt. The flag is cleared to "0" by writing a "0" in a program. (Writing a "1" has no effect. Nor is
it cleared to "0" by an oscillation stop or an oscillation restart detection interrupt request acknowledged.)
If when the CM22 bit = 1 an oscillation stop or an oscillation restart is detected, no oscillation
stop, re-oscillation detection interrupts are generated.
Note 5: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine
the main clock status.
Note 6: Effective when the CM07 bit of CM0 register is "0".
Note 7: When the PM21 bit of PM2 register is "1" (clock modification disabled), writing to the CM20 bit has no
effect.
Note 8: When the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is "1" (the CPU clock source is PLL
clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is "0"
under these conditions, oscillation stop, re-oscillation detection interrupt occurs at main clock stop
detection; it is, therefore, necessary to set the CM21 bit to "1" (on-chip oscillator clock) inside the
interrupt routine.
Note 9: Set the CM20 bit to "0" (disable) before entering stop mode. After exiting stop mode, set the CM20 bit
back to "1" (enable).
Note 10: Set the CM20 bit to "0" (disable) before setting the CM05 bit of CM0 register.
Note 11: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
Note 12: When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off),
the CM06 bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Figure 7.5. CM2 Register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b2 b1 b0
Symbol
CM2
Bit symbol
Oscillation stop, re-
CM20
oscillation detection bit
(Notes 7, 9, 10, 11)
System clock select bit 2
CM21
(Notes 2, 3, 6, 8, 11, 12 )
Oscillation stop, re-
CM22
oscillation detection flag
(Note 4)
X
IN
CM23
(Note 5)
Reserved bit
(b5-b4)
Nothing is assigned. When write, set to "0". When read, its
(b6) content is indeterminate.
Operation select bit
CM27
(when an oscillation stop,
re-oscillation is detected)
(Note 11)
page 42 of 402
Address
000C
16
Bit name
0: Oscillation stop, re-oscillation
detection function disabled
1: Oscillation stop, re-oscillation
detection function enabled
0: Main clock or PLL clock
1: On-chip oscillator clock
(On-chip oscillator oscillating)
0: Main clock stop or re-oscillation
not detected
1: Main clock stop or re-oscillation
detected
0: Main clock oscillating
monitor flag
1: Main clock not oscillating
Must set to "0"
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
detection interrupt
7. Clock Generation Circuit
After reset
0X000010
2
Function
RW
RW
RW
RW
RO
RW
RW