Table of Contents
Advertisement
M16C/29 Group
NMI digital debounce register (Note)
b7
Note : Set bit 2 of protect register (Address 000A
P1
digital debounce register
7
b7
Figure 19.6.1. NDDR and P17DDR Registers
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b0
Symbol
NDDR
Assuming that set value =n,
for n = 0 to FEh, NMI / SD pulse whose width is greater than
(V1/8) / ( n + 1) will be input.
For n = FFh, the digital debounce filter is disabled.
All signals are input
Symbol
b0
P17DDR
Assuming that set value =n,
for n = 0 to FEh, INPC17 / INT5 pulse whose width is greater
than (V1/8) / ( n + 1) will be input.
For n = FFh, the digital debounce filter is disabled.
All signals are input
page 320 of 402
Address
After reset
033E
FF
16
16
Function
) to "1" before writing to NDDR.
16
Address
After reset
033F
FF
16
16
Function
19. Programmable I/O Ports
RW
Setting range
00
~FF
16
16
RW
Setting range
RW
00
~FF
16
16
RW
Advertisement
Table of Contents
