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M16C/29 Group
16.9 START Condition Generation Method
When the ES0 bit of the I
"1" to the MST, TRX, and BB bits and "0" to the PIN and low-order bits of the I
register) simultaneously enters the standby status to generate the start condition. The start condition is
generated after writing the slave address data to the I
becomes "000
" and 1-byte S
2
clock mode and high-speed clock mode. Refer to Figure 16.16 Start condition generation timing dia-
gram, and Table 16.8 Start/Stop generation timing table.
Figure 16.14 Start condition generation flow chart
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
2
C0 control register is "1" and the BB flag of the I
are output. The start condition generation timing is different in standard
CL
Interrupt disable
BB=0?
Yes
S10=E0
16
S00=Data
Interrupt enable
page 270 of 402
16. MULTI-MASTER I
2
C0 data shift register. After that, the bit counter
No
Start condition standby status setting
Start condition trigger generation
*Data=Slave address data
2
C bus INTERFACE
2
C0 status register is "0", writing
2
C0 status register (S10
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