Renesas M16C/29 Series Hardware Manual page 52

M16C/29 Group
V o l t a g e D e t e c t i o n R e g i s t e r 1
b 7
0 0 0 0
N O T E S :
V o l t a g e D e t e c t i o n R e g i s t e r 2
b 7
NOTES:
V o l t a g e D o w n D e t e c t i o n I n t e r r u p t R e g i s t e r
b 7
N O T E S :
Figure 5.5.2 VCR Register, VCR2 Register, and D4INT Register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b 6 b 5 b 4 b 3 b 2 b 1 b 0
S y m b o l
0 0 0
V C R 1
Bit Symbol
(b2-b0)
V C 1 3
(b7-b4)
1 . T h e V C 1 3 b i t i s u s e f u l w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o " 1 " ( v o l t a g e d o w n d e t e c t i o n c i r c u i t e n a b l e ) .
T h e V C 1 3 b i t i s a l w a y s " 1 " ( V C C ≥ 4 V ) w h e n t h e V C 2 7 b i t i s s e t t o " 0 " ( v o l t a g e d o w n d e t e c t i o n c i r c u i t d i s a b l e ) .
2 . T h i s r e g i s t e r d o e s n o t c h a n g e a t s o f t w a r e r e s e t , w a t c h d o g t i m e r r e s e t a n d o s c i l l a t i o n s t o p d e t e c t i o n r e s e t .
( 1 )
b 6 b 5 b 4 b 3 b 2 b 1 b 0
S y m b o l
0 0 0 0 0 0
V C R 2
Bit Symbol
( b 5 - b 0 )
V C 2 6
V C 2 7
1. Write to this register after setting the PRC3 bit in the PRCR register to "1" (write enable).
2. To use voltage down detection (hardware reset 2), set the VC26 bit to "1" (reset level detection circuit enable).
3. VC26 bit is disabled in stop mode (the microcomputer is not reset even if the voltage input to VCC pin
becomes lower than Vdet3).
4. Where the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to "1"
(voltage down detection interrupt enable), set the VC27 bit to "1" (voltage down detection circuit enable).
5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
6. The detection circuit does not start operation until td(E-A) elapses after the VC26 bit, or VC27 bit is set to "1".
b 6 b 5 b 4 b 3 b 2 b 1 b 0
S y m b o l
D 4 I N T
B i t S y m b o l
D 4 0
D 4 1
D 4 2
D 4 3
D F 0
D F 1
( b 7 - b 6 )
1 . W r i t e t o t h i s r e g i s t e r a f t e r s e t t i n g t h e P R C 3 b i t i n t h e P R C R r e g i s t e r t o " 1 " ( w r i t e e n a b l e ) .
2 . U s e f u l w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o " 1 " ( v o l t a g e d o w n d e t e c t i o n c i r c u i t e n a b l e d ) . I f t h e
V C 2 7 b i t i s s e t t o " 0 " ( v o l t a g e d o w n d e t e c t i o n c i r c u i t d i s a b l e ) , t h e D 4 2 b i t i s s e t t o " 0 " ( N o t d e t e c t ) .
3 . T h i s b i t i s s e t t o " 0 " b y w r i t i n g a " 0 " i n a p r o g r a m . ( W r i t i n g a " 1 " h a s n o e f f e c t . )
4 . I f t h e v o l t a g e d o w n d e t e c t i o n i n t e r r u p t n e e d s t o b e u s e d t o g e t o u t o f s t o p m o d e a g a i n a f t e r o n c e u s e d f o r t h a t
p u r p o s e , r e s e t t h e D 4 1 b i t b y w r i t i n g a " 0 " a n d t h e n a " 1 " .
5 . T h e D 4 0 b i t i s e f f e c t i v e w h e n t h e V C 2 7 b i t = 1 . T o s e t t h e D 4 0 b i t t o " 1 , " s e t b i t s i n t h e f o l l o w i n g o r d e r .
( a ) S e t t h e V C 2 7 b i t t o " 1 " .
( b ) W a i t f o r t d ( E – A ) u n t i l t h e d e t e c t i o n c i r c u i t i s a c t u a t e d .
( c ) W a i t f o r t h e s a m p l i n g t i m e . ( S e e T a b l e 6 . 2 S a m p l i n g P e r i o d)
( d ) S e t t h e D 4 0 b i t t o " 1 " .
page 32 of 402
A d d r e s s A f t e r R e s e t
0 0 1 9 h 0 0 0 0 1 0 0 0 b
B i t N a m e
R e s e r v e d B i t Set to "0"
( 1 ) 0 : V C C < V d e t 4
V o l t a g e D o w n M o n i t o r F l a g
1 : V C C ≥ V d e t 4
R e s e r v e d B i t Set to "0"
A d d r e s s A f t e r R e s e t
0 0 1 A h 0 0 h
B i t N a m e
R e s e r v e d B i t Set to "0"
0 : D i s a b l e r e s e t l e v e l d e t e c t i o n
( 2 , 3 , 6 )
R e s e t L e v e l M o n i t o r B i t
c i r c u i t
1 : E n a b l e r e s e t l e v e l d e t e c t i o n
c i r c u i t
0: Disable voltage down
V o l t a g e D o w n M o n i t o r
detection circuit
( 4 , 6 )
B i t
1: Enable voltage down
detection circuit
( 1 )
A d d r e s s A f t e r R e s e t
0 0 1 F h 0 0 h
B i t N a m e
V o l t a g e D o w n D e t e c t i o n
0 : D i s a b l e
( 5 )
I n t e r r u p t E n a b l e B i t 1 : E n a b l e
S T O P M o d e D e a c t i v a t i o n 0 : D i s a b l e ( d o n o t u s e t h e p o w e r
s u p p l y d o w n d e t e c t i o n
( 4 )
C o n t r o l B i t
i n t e r r u p t t o g e t o u t o f s t o p m o d e )
1 : E n a b l e ( u s e t h e v o l t a g e
d o w n d e t e c t i o n i n t e r r u p t t o g e t
o u t o f s t o p m o d e )
V o l t a g e C h a n g e D e t e c t i o n
0 : N o t d e t e c t e d
( 2 )
F l a g 1 : V d e t 4 p a s s i n g d e t e c t i o n
0 : N o t d e t e c t e d
W D T O v e r f l o w D e t e c t F l a g
1 : D e t e c t e d
b 5b 4
S a m p l i n g C l o c k S e l e c t B i t
0 0 : C P U c l o c k d i v i d e d b y 8
0 1 : C P U c l o c k d i v i d e d b y 1 6
1 0 : C P U c l o c k d i v i d e d b y 3 2
1 1 : C P U c l o c k d i v i d e d b y 6 4
N o t h i n g i s a s s i g n e d . W h e n w r i t e , s e t t o " 0 " . W h e n r e a d , i t s
c o n t e n t i s " 0 " .
( 2 )
F u n c t i o n R W
RW
RO
RW
( 5 )
F u n c t i o n R W
R W
R W
R W
F u n c t i o n R W
R W
R W
(3)
RW
(3)
RW
R W
R W
5. Reset