Renesas M16C/29 Series Hardware Manual page 252

M16C/29 Group
A/D trigger control register (Note 1)
b7 b6 b5 b4 b3
0
Note 1: If ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 15.1.6.3 ADTRGCON Register in Simultaneous Sample Sweep Mode
TRG TRG1
-
0
-
1
1
0
1
1
Note 1. A count can be started for Timer B2, Timer B2 interrupt generation frequency
setting counter underflow or the INT5 pin falling edge as count start
conditions of Timer B0.
Note 2. Select Timer B2 or Timer B2 interrupt generation frequency setting counter
using the TB2SEL bit in the TB2SC register.
Table 15.1.6.2 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b2 b1 b0
Symbol
0 1
ADTRGCON
Bit symbol
A/D Operation Mode
SSE
Select Bit 2
A/D Operation Mode
DTE
Select Bit 3
AN0 Trigger Select Bit
HPTRG0
AN1 Trigger Select Bit
HPTRG1
Nothing is assigned. When write, set to "0".
(b7-b4)
When read, its content is "0".
TRIGGER
HPTRG0
Software trigger
-
Timer B0 underflow (Note 1)
1
0
AD
TRG
Timer B2 or Timer B2 interrupt generation frequency
0
setting counter underflow (Note 2)
page 232 of 402
Address After reset
03D2 00
16
Bit name
1 : Simultaneous sample sweep mode
or delayed trigger mode 0, 1
0 : Any mode other than delayed trigger
mode 0,1
Refer to Table 15.1.6.2 Trigger Select
Bit Setting in Simultaneous Sample
Sweep Mode
Set to "0" in simultaneous sample
sweep mode
15. A/D Converter
16
Function RW
RW
RW
RW
RW