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M16C/29 Group
I 2 C0 data shift register
write signal
S
CL
S
DA
Figure 16.16 Start condition generation timing diagram
2
I
C0 data shift register
write signal
S
CL
S
DA
Figure 16.17 Stop condition generation timing diagram
Table 16.8 Start/Stop generation timing table
Item
Start/Stop condition generation
select bit
Setup
time
hold
time
Note 1. Actual time at the time of V
As mentioned above, Writing "1" to MST and TRX bits.
Writing "1" or "0" to the BB bit, writing "0" to the PIN and low-order 4 bits, simultaneously set up the START
or STOP condition standby. It releases the S
STOP condition standby. The signal writing to data shift register triggers the generation of START/STOP
conditions. In the case of setting the MST, and the TRX to "1" without generating a START/STOP condi-
tion. Write "1" to the low-order 4 bits simultaneously. Table16.9 shows the function of writing to the status
register.
Table 16.9 The function of writing to status register
The value of the data writing to status register
MST TRX BB PIN AL AAS AS0 LRB
1
1
1
0
1
1
0
0
0/1
0/1
-
0
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Setup
Hold
time
time
Hold
Setup
time
time
"0"
"1"
"0"
"1"
= 4MHz, The contents in () denote cycle numbers.
IIC
0
0
0
0
0
0
0
0
1
1
1
1
page 272 of 402
16. MULTI-MASTER I
Standard clock mode
5.0µs (20 cycles)
13.0µs (52 cycles)
5.0µs (20 cycles)
13.0µs (52 cycles)
in the START condition standby, sets the S
DA
Function
Setting up the START condition stand by in master transmit mode
Setting up the STOP condition stand by in master transmit mode
Setting up each communication mode (refer to Chapter 16.5 I
2
C bus INTERFACE
High-speed clock mode
2.5µs (10 cycles)
6.5µs (26 cycles)
2.5µs (10 cycles)
6.5µs (26 cycles)
to "L" in the
DA
2
C status register)
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